The present invention relates to a data communication and more particularly to monitoring an Asynchronous Transfer Mode cell bus.
The Asynchronous Transfer Mode (ATM) is the technology selected by the Consultative Committee on International telephone and Telegraph (ITU) International standards organization (now called the ITU-T) to realize a Broadband Integrated Services Digital Network (B-ISDN). ATM is a very high speed transmission technology utilized in data communication. A general concept of ATM is disclosed by Harry Neviton in Newton""s Telecom Dictionary, Flatiron Publishing, pp. 67-8, 1998 and is fully incorporated herein.
ATM is a high bandwidth, low-decay, connection-oriented, packet-like switching and multiplexing technique. The usable capacity is segmented into 53 fixed size cells, consisting of header and information fields, allocated to services on demand. The small, fixed length cells require lower processing overhead and allow higher transmission speeds than traditional packet switching methods. Also, ATM automatically adjusts the network capacity to meet the system needs and can handle data, voice, video and television signals.
All broadband transmissions (whether audio, data, imaging or video) are divided into the fixed length cells and routed across an ATM network consisting of links connected by ATM switches. Each ATM link comprises a constant stream of ATM cell slots into which transmissions are placed or left idle, if unused. The cell-switching technology of ATM combines the best advantages of both circuit-switching (for constant bit rate services such as voice and image) and packet-switching (for variable bit rate services such as data and full motion video) technologies.
Particularly, each cell consists of 53 eight-bit bytes, called octets, wherein five octets are header field and the remaining 48 octets are user data. The header contains data that identifies the related cell, a logical address that identifies the routing, header error correction bits for priority handling and network management functions. The user data contains the xe2x80x9cpayloadxe2x80x9d or the information to be transmitted.
An ATM switching system in the related art includes a bus master and a plurality of bus slaves connected to the bus master. Also, a system manager may monitor the status of ATM cell buses utilizing a Cyclic Redundancy Check (CRC). Namely, the cell buses are monitored during the transmission and reception of Packets by periodically requesting and receiving responses to analyze the CRC value of the transmitted and received data.
As an error detection method for detecting group error in the transmitted data, the CRC utilizes polynomial codes for error detection as well as the minimum bits required for expressing the data to detect errors. For CRC, additional bits need not be attached to each character, like a parity checking method. However, a Frame Check Sequence (FCS) calculated based upon the actual contents of a frame is attached to the end of the frame and transmitted. Accordingly, generation of polynomial to calculate the FCS is required.
As described above, CRC allows a system manager to periodically detect errors in the ATM switching system. Therefore, errors cannot be detected as the errors occur in between the periods while the ATM switching system is in operation.
An object of the present invention is to solve at least the problems and disadvantages of the related art.
Another object of the present invention is to provide a hardware based method of monitoring ATM cell buses.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
To achieve the objects and in accordance with the purposes of the invention, as embodied and broadly described herein,